Search - verilog CPU

[VHDL-FPGA-Verilog] uart

Description: UART verilog 代码，内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Platform: | Size: 15360 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] i2c

Description: I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
Platform: | Size: 13312 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] alu

Description: this is source code in verilog for arithmatic logic unit for RISC cpu
Platform: | Size: 63488 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] RISCcpu

Description: this verilog model of RISC CPU-this is verilog model of RISC CPU
Platform: | Size: 141312 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

Description: This a verilog code of single cycle mips-This is a verilog code of single cycle mips
Platform: | Size: 587776 | Author: hualin | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
Platform: | Size: 5579776 | Author: Po | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.
Platform: | Size: 79872 | Author: 书柬图章 | Hits:

Description: 本程序主要完成cpu的几个主功能模块的开发，开发语言为verilog硬件语言，基本能模拟cpu的核心功能！-The program mainly to complete the main features of several cpu module development, hardware development language for the verilog language, the basic core functionality can simulate the cpu!
Platform: | Size: 5120 | Author: 赵洵 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
Platform: | Size: 4096 | Author: ysshr | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] risc_cup

Description: 精简指令集CPU的VERILOG语言实现，很有用-RISC CPU the VERILOG language, very useful
Platform: | Size: 474112 | Author: 侯勇 | Hits:

[VHDL-FPGA-Verilog] DW8051_core

Description: 8051的内核源码,用verilog HDL写成，已验证功能正确-open core fo 8051 cpu
Platform: | Size: 438272 | Author: gaoming | Hits:

[VHDL-FPGA-Verilog] CPU

Description: cup developed by scope verilog
Platform: | Size: 9216 | Author: wei chenghao | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
Platform: | Size: 1190912 | Author: sunying | Hits:

[VHDL-FPGA-Verilog] Verilog-HDLTOP-DOWN

Description: 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
Platform: | Size: 43008 | Author: 刘鹏飞 | Hits:

[VHDL-FPGA-Verilog] 32bitcpu

Description: 用verilog写的32位CPU源码，通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率，大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码，过程文件，readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. And through the Lookahead algorithm improve the efficiency, significant savings in computing time. ASC process can be simulated by its internal circuit. Code, process documents, readme in the folder
Platform: | Size: 13528064 | Author: 杨岩 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用Verilog语言编写的单周期cpu，实现的指令有 add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu, sltiu, blez, j.
Platform: | Size: 5120 | Author: yejunjian | Hits:

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[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] RISCcpu

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] NET2

[VHDL-FPGA-Verilog] risc_cup

[VHDL-FPGA-Verilog] DW8051_core

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] Verilog-HDLTOP-DOWN

[VHDL-FPGA-Verilog] 32bitcpu

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] RISC_cpu

[VHDL-FPGA-Verilog] mdio

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